1. Field of the Invention
The present relates generally to bus driver circuit. More specifically, the invention relates to a bus driver circuit permitting adjustment of transition period of rising up and falling down of a transmitting data output and whereby realizing high speed transmission of the transmitting data.
2. Description of the Related Art
Conventional high speed bus driver for transmission of a transmitting data has different through rate (transition period in rising up of the transmitting data output) for efficiently performing high speed signal transmission depending upon the kind and nature of the data waveform to be transmitted, signal propagation speed and installation condition of other associated boards.
Accordingly, in order to perform signal transmission efficiency, it is necessary to select optimal through rate depending upon the kind and nature of the data waveform to be transmitted, signal propagation speed and installation condition of other associated boards.
However, the through rate of this type of bus driver is significantly depends on the performance of a transistor included therein. Therefore, the conventional bus driver circuit has no function for adjusting the through rate or has simple adjustment function discussed below.
One example of the conventional bus driver circuit which permits adjustment of the through rate, has been disclosed in Laid-Open application No. 2-122725. In this publication, there is a disclosure for the bus driver circuit, in which the through rate is adjusted by a control terminal and N-channel transistor and P-channel transistor. In concrete, when a voltage of high potential (H) is applied to the control terminal, the N-channel transistor and the P-channel transistor are turned ON. By this, the N-channel of an inverter is strengthened so that the gate of the P-channel transistor may turn into low potential (L) at high speed. As set forth above, in this prior art, the through rate of the output buffer is adjusted.
Thus, the conventional bus driver circuit does not have the through rate adjusting function or has only a simple adjusting function. Therefore, it is not possible to efficiently perform high speed transmission of the data waveform at an optimal through rate depending upon the kind and nature of the data waveform to be transmitted, signal propagation speed and installation condition of other associated boards. Also, the foregoing conventional bus driver circuit having the through rate adjusting function, adjustment of the through rate is permitted between two levels. Therefore, in order to obtain optimal through rate, the design has to be differentiated per the system to apply.
Therefore, it has been desired a bus driver circuit which permits multi-level adjustment of the through rates.
Next, discussion will be given for the prior art in a signal output circuit for outputting a signal to be input to the bus driver circuit.
At first, in advance of discussion for the prior art, the general construction of a bus transmission path will be discussed with reference to the drawing, particularly to FIG. 12. As shown in FIG. 12, a plurality of bus transmission paths 303 are provided on a mother board 300. Also, on the mother board 300, a plurality of connectors 301 are mounted, To the connectors 301, substrates 302 are connected. Thus, the internal circuit of the substrates 302 are connected to the bus transmission paths. Each of the substrates 302 receives and transmits signals via the bus transmission paths.
A characteristic impedance of the bus transmission paths may be varied depending upon the various factors. A major factor to cause variation in the number of substrates to be installed to the connector 301 is yield in fabrication. Amongst, discussion will be given for variation of the impedance with reference to the drawing, particularly to FIG. 12,
In the construction of the bus transmission path as illustrated in FIG. 12, the number of substrate 302 to be connected to the bus transmission path 303 is not constant. For example, in FIG. 13, only substrates 302 at both ends are connected to the connector 301. Therefore, number of the substrate is two. On the other hand, in FIG. 14, the number of the substrate to be installed becomes seven.
By variation of the number of the installed substrates, the characteristic impedance of the bus transmission path 303 is varied. In order to show this, the approximated characteristic impedances of respective constructions of FIGS. 13 and 14 are calculated.
In the bus transmission path of the construction shown in FIG. 12, it is assumed that the distance between the connectors 301 is 1 inch (2.54 cm), the characteristic impedance of the bus transmission path in the case where no substrate is installed is Z0:0.75xcexa9 and propagation delay period is t=7 ns/m. At this time, an inductance component L0 and capacitance component C0 are approximately calculated as 13.5 nH/inch and 2.36 Pf/inch.
Here, assuming that 25 pF of the capacitance component is increased per each substrate 302, the characteristic impedance Z1 of the bus transmission path 303 in the construction of FIG. 13 can be calculated as 32.2xcexa9. On the other hand, the characteristic impedance Z2 of the bus transmission path 303 in the construction of FIG. 14 becomes 20.5xcexa9. Namely, when the construction of FIG. 14 is constructed by adding five substrates 302 for the construction of FIG. 13, the characteristic impedance is lowered in the extent of 14.7xcexa9.
In the discussion given hereabove, variation of the characteristic impedance is theoretically calculated with employing approximation for simplification. However, in practice, it is difficult to predict variation of the characteristic impedance in advance of actual installation of the substrate. For example, the characteristic impedance may be variable not only depending upon the number of substrate to be installed in the bus transmission path but also depending upon the position of installation of the substrate. Thus, the characteristic impedance of the bus transmission path is variable depending upon various factors. Then, associating with variation of the characteristic impedance, the signal waveform to be propagated on the bus transmission path may be differentiated.
For example, in case of a pulse wave, when the characteristic impedance of the bus transmission path is excessively large, the rising up period of the pulse becomes long. On the other hand, when the characteristic impedance is too small, ringing may be caused. Ringing is a transitional vibration of the waveform to be caused by abrupt rising up of the pulse and can be a cause of malfunction.
Beside, in order to propagate signal at high speed, signal has to be maintained at constant waveform. Therefore, the characteristic impedance of the bus transmission path has to be corrected to be a given constant value.
One example of the conventional signal output circuit having an adjusting function for the characteristic impedance of the bus transmission path is shown in FIG. 15. With reference to FIG. 15, between the output portion 311 for outputting the signal and the bus transmission path 333, a resistor 351 is connected. In this signal output circuit, by varying the resistance of the resistor 351, the characteristic impedance is adjusted to shape the signal waveform into a desired shape. The resistance of the resistor 351 is determined depending upon the characteristic impedance of the bus transmission path 333.
However, in the above-mentioned conventional signal output circuit, when the characteristic impedance is varied by modification of the installation condition of the substrates in the bus transmission path, it becomes necessary to exchange the resistor per se in order to vary the resistance value to make handling cumbersome.
Also, as set forth above, it is difficult to even theoretically predict the characteristic impedance of the bus transmission path. Therefore, the resistance value of the resistor to be employed in the signal output circuit has to be obtained through experiments. At this time, it is required to repeat cumbersome operation to exchange the resistors.
It is the first object of the present invention to provide a bus driver circuit which can solve the problems set forth above, and permits selection of an optimal through rate for enabling efficient and high speed transmission of data depending upon the kind and nature of the data waveform to be transmitted, signal propagation speed and installation condition of other associated boards.
Second object of the present invention is, in addition to the foregoing first object, to provide a signal output circuit for obtaining a resistance value depending upon a characteristic impedance of a bus transmission path with simple operation.
According to the first aspect of the invention, a bus driver circuit comprises:
a plurality of MOS transistors connected in series between a data input terminal and a data output terminal, and a plurality of controlling MOS transistors;
sources of the plurality of MOS transistors being connected to drains of the plurality of controlling MOS transistors; and
gates of the plurality of MOS controlling transistors to control signal source means for selectively turning ON and OFF the plurality of controlling transistors.
Preferably, N in number of the MOS transistors and M in number of controlling MOS transistors are provided, in which M is smaller than N;
drains of first to Nth MOS transistors are connected to the data output terminal and gates thereof are connected to the data input terminal;
sources of first to Mth controlling MOS transistors are connected to the drains of first to Mth MOS transistors; and
gates of (M+1)th to Nth MOS transistors are connected to the ground;
the gates of the first to Mth controlling MOS transistors are connected to the control signal source means to respectively receive first to Mth control signals for turning ON and OFF the first to Mth controlling MOS transistors; and
the sources of the first to Mth controlling MOS transistors are connected to the ground.
Between the sources of the first to Mth controlling MOS transistors and the ground, first to Mth resistors may be connected, respectively.
According to the second aspect of the invention, a bus driver circuit comprises:
a plurality of NPN transistors connected in series between a data input terminal and a data output terminal, and a plurality of controlling NPN transistors;
sources of the plurality of NPN transistors being connected to drains of the plurality of controlling NPN transistors; and
gates of the plurality of NPN controlling transistors to control signal source means for selectively turning ON and OFF the plurality of controlling transistors.
In the preferred construction, N in number of the NPN transistors and M in number of controlling NPN transistors are provided, in which M is smaller than N;
drains of first to Nth NPN transistors are connected to the data output terminal and gates thereof are connected to the data input terminal;
sources of first to Mth controlling NPN transistors are connected to the drains of first to Mth NPN transistors; and
gates of (M+1)th to Nth NPN transistors are connected to the ground;
the gates of the first to Mth controlling NPN transistors are connected to the control signal source means to respectively receive first to Mth control signals for turning ON and OFF the first to Mth controlling NPN transistors; and
the sources of the first to Mth controlling NPN transistors are connected to the ground.
Between the sources of the first to Mth controlling NPN transistors and the ground, first to Mth resistors may be connected, respectively.
According to the third aspect of the invention, a device driver circuit comprises:
an input terminal inputting an input signal;
a delay circuit for outputting a delayed signal generated by delaying the input signal from the input terminal for a selected one of a plurality of preset delay periods;
an output circuit for outputting an output signal with superimposing the input signal from the input terminal and the delayed signal from the delay circuit; and
an output terminal outputting the output signal from the output circuit.
The delay circuit may include a plurality of delay elements and selection means for selecting one or more delay elements among a plurality of delay elements in arbitrary combination. The selection means may comprise a selector which received a signal past through at least one delay elements and a signal not past through the delay element, and selectively output one of the signals.
The output circuit may include first NPN transistor having base connected to the input terminal, emitter is connected to the ground and collector, and second NPN transistor which has base connected to the delay circuit, emitter is connected to the ground and the collector is connected to the output terminal. The output circuit may include first MOS transistor having base connected to the input terminal, emitter is connected to the ground and collector, and second MOS transistor which has base connected to the delay circuit, emitter is connected to the ground and the collector is connected to the output terminal.
According to the fourth aspect of the invention, a signal output device comprises:
an output portion for outputting a signal to a bus transmission line; and
a variable impedance position provided between the output portion and the bus transmission line and generates an arbitrary impedance.
The variable impedance means may include a resistor for adding resistance for the signal output from the output portion and including variable resistor portion arbitrary variable of the resistance value thereof. The variable resistor portion may comprise a resistor connected in parallel and having mutually distinct resistance values, and a selector for selecting one of a plurality of the resistors. Also, the variable resistor may include a plurality of resistors; and selection means for selecting one or more resistors in an arbitrary combination among a plurality of registers.
The selection means may be a selector receiving a signal past through at least one resistor and a signal not past through the signal processing means and selecting one of the signals.
The variable resistance portion may include the plurality of resistors having mutually different resistances. The variable resistor portion may include a plurality of resistor blocks generating a predetermined resistance value at a specific pattern of input selection signal and becoming conductive at other patterns of the input selection signal. The plurality of resistor blocks may be connected in series. Also. the plurality of resistor blocks may generate mutually different resistance values.
When a minimum resistance value among resistance values of a plurality of resistor blocks is taken as minimum resistance value, respective resistance values of the plurality of resistor blocks are powers of 2 of the minimum resistance value. Also, the plurality of resistance blocks includes a first resistance block having the minimum resistance value and a second resistance block having a resistance value twice of the minimum resistance value.
According to a fifth aspect of the invention, a bus driver circuit comprises:
a plurality of MOS transistors connected in series between a data input terminal and a data output terminal, a plurality of controlling MOS transistors, and a signal output circuit having an output portion for generating a signal and a variable impedance means for arbitrarily generating impedance;
source of the plurality of MOS transistors being connected to drains of the controlling MOS transistors;
gates of the plurality of controlling MOS transistors being connected to a control signal source for receiving a plurality of control signals respectively for selectively turning ON and OFF the plurality of controlling MOS transistors; and
the data input terminal being connected to the signal output circuit.
According to a sixth aspect of the invention, a bus driver circuit comprises:
a plurality of NPN transistors connected in series between a data input terminal and a data output terminal, a plurality of controlling NPN transistors, and a signal output circuit having an output portion for generating a signal and a variable impedance means for arbitrarily generating impedance;
source of the plurality of NPN transistors being connected to drains of the controlling NPN transistors;
gates of the plurality of controlling NPN transistors being connected to a control signal source for receiving a plurality of control signals respectively for selectively turning ON and OFF the plurality of controlling NPN transistors; and
the data input terminal being connected to the signal output circuit.
According to a seventh aspect of the invention, a device driver circuit comprises:
an input terminal for inputting an input signal;
a delay circuit for outputting a delayed signal generated by delaying the input signal from the input terminal for a selected one of a plurality of preset delay periods;
an output circuit for outputting an output signal with superimposing the input signal from the input terminal and the delayed signal from the delay circuit;
an output terminal outputting the output signal from the output circuit; and
a signal output circuit having an output portion for outputting a signal and a variable impedance means for arbitrarily generating an impedance, the signal output circuit being connected to the input terminal.